The timing evaluation signifies the presence of additional ranges of combinational logic, however  I solely have one layer of combinational logic.I do not know the place the additional combinational logic is?

The really useful violation decision strategies within the time collection evaluation report are as follows.

The code for this path is as follows.Amongst them, clk_6 is a 500MHz clock generated by a PLL.

all the time@(posedge clk_6 or negedge rst) start
       if(!rst) start
                         pps_6<=1’d0;
                  finish
       else start
                if(delay_2==4’d5)
                 start
                         pps_6=pps_coarse;finish
                 else start
                           pps_6<=1’b0;finish
               finish
       finish

Beneath is the timing evaluation for the error path.