Hello Crew,

       I’ve compiled the design with ddr3,nios ii processor, avalon mm and different ip interfaces. I’ve used the ddr3 reminiscence with 400 mhz and different interface makes use of afi_half_clk like that I’ve related in qsys system. for fitter i’ve warnings. Are you able to please give answer for these warnings.

Warning (15400): WYSIWYG primitive “Mux24:inst|Mux24_cpu:cpu|Mux24_cpu_cpu:cpu|Mux24_cpu_cpu_nios2_oci:the_Mux24_cpu_cpu_nios2_oci|Mux24_cpu_cpu_nios2_ocimem:the_Mux24_cpu_cpu_nios2_ocimem|Mux24_cpu_cpu_ociram_sp_ram_module:Mux24_cpu_cpu_ociram_sp_ram|altsyncram:the_altsyncram|altsyncram_qid1:auto_generated|ram_block1a11” has a port clk0 that’s caught at GND

related warnings are listed extra in warnings tab.