Hi there,

I’ve a query concerning the interpretation of the readyAllowance property in back-pressured Avalon ST interfaces. It might be nice if somebody may assist me out.

The Avalon specification defines readyAllowance in Sec. 5.4 as follows:

Defines the variety of transfers that the sink can seize after prepared is deasserted.

When readyAllowance = 0, the sink can’t settle for any transfers after prepared is deasserted. If readyAllowance = <n> the place <n> is bigger than 0, the sink can settle for as much as <n> transfers after prepared is deasserted.

Based on my studying, this definition doesn’t require these potential <n> transfers to be consecutive.

For instance,  trying on the timing diagram beneath and assuming readyLatency=2 (Based on the specification, if nothing else is specified, readyAllowance can even be 2):

• The primary switch (cycle 0 to three) must be legitimate. Actually, Fig. 30 (Sec. 5.9.2) of the specification exhibits an equal switch.
• However what about the second (cycle 5 to 9)? prepared is de-asserted in cycle 6 and a couple of transfers comply with.Is there one thing within the definitions that doesn’t enable this?

Any assistance on this might be significantly appreciated; thanks upfront.