Howdy Intel boards,

I am attempting to make use of the Transceiver toolkit on my Stratix 10 GX H-tile devkit, however I am having issues making it work. I am following this video for directions:

https://www.youtube.com/watch?app=desktop&v=bwhyJuphy8I

This tutorial appears to be for Quartus 18.1, however I am utilizing 22.4.

I’ve applied a 25GBps transceiver with these settings within the dynamic reconfiguration tab:

I am unsure if the “Use AVMM clock and reset ports solely” is appropriate. If that is not chosen, there is a bunch of ports that I do not know the way or what to connect with.

Within the ATX pll, I exploit these settings:

I join the `reconfig_clk` ports on each IPs to a 100MHz clock and the reset to my world reset (unsure if that is appropriate; it isn’t talked about within the video). After efficiently compiling the design and programming the board, I opened the “System debugging toolkits” (the transceiver toolkit appears to not be seperate anymore.) and loaded my design there. This is what I see:

From what I can inform, the system console can connect with the machine, however it may possibly’t talk with the PHY. Do I want a NIOS for this? I would want to do with out if doable.

Are you able to assist me remedy this? I would like to supply eye diagrams for my transceiver in addition to get the BER and optimum analog settings for my implementation.

If it is useful, I can present a qar archive of my challenge.

Thanks in your help.