Hola con todos, tengo instalado Quartus en debian, y al momento de simular en “College Program VWF” se queda estancado y no termina el proceso. La verdad no tengo ni thought de como solucionar

Figuring out the situation of the ModelSim executable…

Utilizing: /dwelling/manuel/intelFPGA_lite/19.1/modelsim_ae/linuxaloem/

To specify a ModelSim executable listing, choose: Instruments -> Choices -> EDA Software Choices
Observe: if each ModelSim-Altera and ModelSim executables can be found, ModelSim-Altera will probably be used.

**** Producing the ModelSim Testbench ****

quartus_eda –gen_testbench –tool=modelsim_oem –format=vhdl –write_settings_files=off reg_s_p1 -c reg_s_p1 –vector_source=”/dwelling/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/Waveform7.vwf” –testbench_file=”/dwelling/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/Waveform7.vwf.vht”

Information: *******************************************************************Information: Working Quartus Prime EDA Netlist Author Information: Model 19.1.0 Construct 670 09/22/2019 SJ Lite Version Information: Copyright (C) 2019 Intel Company. All rights reserved. Information: Your use of Intel Company’s design instruments, logic features Information: and different software program and instruments, and any companion logic Information: features, and any output recordsdata from any of the foregoing Information: (together with gadget programming or simulation recordsdata), and any Information: related documentation or info are expressly topic Information: to the phrases and situations of the Intel Program License Information: Subscription Settlement, the Intel Quartus Prime License Settlement, Information: the Intel FPGA IP License Settlement, or different relevant license Information: settlement, together with, with out limitation, that your use is for Information: the only goal of programming logic gadgets manufactured by Information: Intel and bought by Intel or its approved distributors. Please Information: discuss with the relevant settlement for additional particulars, at Information: https://fpgasoftware.intel.com/eula. Information: Processing began: Mon Mar 18 01:01:27 2024Info: Command: quartus_eda –gen_testbench –tool=modelsim_oem –format=vhdl –write_settings_files=off reg_s_p1 -c reg_s_p1 –vector_source=”/dwelling/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/Waveform7.vwf” –testbench_file=”/dwelling/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/Waveform7.vwf.vht”Warning (18236): Variety of processors has not been specified which can trigger overloading on shared machines. Set the worldwide project NUM_PARALLEL_PROCESSORS in your QSF to an acceptable worth for greatest efficiency.

Accomplished efficiently.

**** Producing the purposeful simulation netlist ****

quartus_eda –write_settings_files=off –simulation –functional=on –flatten_buses=off –tool=modelsim_oem –format=vhdl –output_directory=”/dwelling/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/” reg_s_p1 -c reg_s_p1

Information: *******************************************************************Information: Working Quartus Prime EDA Netlist Author Information: Model 19.1.0 Construct 670 09/22/2019 SJ Lite Version Information: Copyright (C) 2019 Intel Company. All rights reserved. Information: Your use of Intel Company’s design instruments, logic features Information: and different software program and instruments, and any companion logic Information: features, and any output recordsdata from any of the foregoing Information: (together with gadget programming or simulation recordsdata), and any Information: related documentation or info are expressly topic Information: to the phrases and situations of the Intel Program License Information: Subscription Settlement, the Intel Quartus Prime License Settlement, Information: the Intel FPGA IP License Settlement, or different relevant license Information: settlement, together with, with out limitation, that your use is for Information: the only goal of programming logic gadgets manufactured by Information: Intel and bought by Intel or its approved distributors. Please Information: discuss with the relevant settlement for additional particulars, at Information: https://fpgasoftware.intel.com/eula. Information: Processing began: Mon Mar 18 01:01:28 2024Info: Command: quartus_eda –write_settings_files=off –simulation=on –functional=on –flatten_buses=off –tool=modelsim_oem –format=vhdl –output_directory=”/dwelling/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/” reg_s_p1 -c reg_s_p1Warning (18236): Variety of processors has not been specified which can trigger overloading on shared machines. Set the worldwide project NUM_PARALLEL_PROCESSORS in your QSF to an acceptable worth for greatest efficiency.Information (204019): Generated file reg_s_p1.vho in folder “/dwelling/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim//” for EDA simulation toolInfo: Quartus Prime EDA Netlist Author was profitable. 0 errors, 1 warning Information: Peak digital reminiscence: 1101 megabytes Information: Processing ended: Mon Mar 18 01:01:28 2024 Information: Elapsed time: 00:00:00 Information: Complete CPU time (on all processors): 00:00:00

Accomplished efficiently.

**** Producing the ModelSim .do script ****

/dwelling/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/reg_s_p1.do generated.

Accomplished efficiently.

**** Working the ModelSim simulation ****

/dwelling/manuel/intelFPGA_lite/19.1/modelsim_ae/linuxaloem//vsim -c -do reg_s_p1.do