No.  Delay is inherent to indicators reaching their vacation spot so you can not take away these delays.  I believe you are misinterpreting “simulation” right here.  For a practical simulation to confirm the design is working functionally, sure, delays are usually not taken under consideration.  It simply appears at how the logic itself features (i.e. ensure a 1 ANDed with one other sign going excessive produces a 1).

The concept behind timing evaluation to to ensure that a receiving/latch register accurately latches in knowledge, primarily based on the register’s setup and maintain timing necessities, which is inherent to the silicon.  As such, the delays for when the clocks arrive on the launch and latch registers in addition to the information delay to get the information from the launch register to the latch register are required for such an evaluation.

Whereas tougher to arrange and it takes for much longer to run (and it is not supported for each machine), a gate-level simulation (in a third occasion simulation device) does take a look at performance and does take knowledge delays under consideration.  Between an RTL practical simulation and timing evaluation, you totally confirm your design whereas avoiding having to carry out a gate-level sim.