Hello,

I simply improve my venture for a Stratix 10 MX FPGA from 20.4 to 22.4.

With 20.4 the design run was profitable however after upgrading to 22.4 I see planning errors with the identical RTL / IP set:

Error(22412): The design requires at the very least 3 components of sort AIB_3VIO_OE however the system has solely 2. 
Information(22415): AIB_3VIO_OE node(s) not related to an IP require components of this sort: 
Information(22414): Node: AIB_3VIO_OE AIB_3VIO_CELL~u_i2c_master|u_i2c_master_top|byte_ctrl|bit_ctrl|isda_oen. 
Information(22414): Node: AIB_3VIO_OE AIB_3VIO_CELL~u_i2c_master|u_i2c_master_top|byte_ctrl|bit_ctrl|iscl_oen. 
Information(22414): Node: AIB_3VIO_OE AIB_3VIO_CELL~u_ltc2226_clk_output_gpio_top|u_ltc2226_clk_output_gpio|ltc2226_clk_output_gpio|core|i_loop[0].altera_gpio_bit_i|output_buffer.obuf~quartus_inserted_3vio_obuf_oe_wirelut. 

The GPIO for I2C grasp SDA/SCL is outlined as bidirectional with open-drain and output allow chosen:

LTC2226 clock output GPIO does is simply configured for output:

The OEN path is applied in 22.4 which was not the case with 20.4
which does not appear to be allowed and leads to an error (all three GPIO IP information are hooked up).

– May you assist me to resolve that downside? 

– Do I would like any extra qsf setting for this port which was not crucial in 20.4?

Greatest regards, 

Michael