Hello

I am engaged on CycloneVsoc Dev Package baremetal system

Now I wish to use F2H sdram to transmit my knowledge.

The draft system Interconnection:

HPS host grasp

  |     

  |    host order

  |

SelfIP write  ——-ST———-| SGDMA |——–MM————->  SDRAM

SelfIP learn  <——-ST———| SGDMA |——–MM————-     SDRAM

do I have to switch the Endian for the SGDMA?

or is there any setting to let avalon ST utilizing little endian?

As for HPS,

HPS view of mmap is MPU one, so the tackle of SDRAM is from 0x00100000 to 0xC0000000, in response to HPS UG,

is that the bodily tackle or vertual one?

what is that this SDRAM stands for ,? Is it the ddr3 chip on this board?

Whether it is, is that the place the place my codes are?

how ought to I put/get knowledge to sdram inside and past this scope from HPS? 

CycloneVsoc tackle map

Reguards

Alex