Use L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP. The “datapath Choices” and Widespread PMA Choices” configurations are proven within the hooked up footage.Utilizing PRBS to check the bit error fee on the velocity of 16Gpbs, it’s discovered that there’s a excessive bit error fee.

I used the default values for “RXPMA” and “Improve PCS” and “PCS-Core Interface” and “Analog PMA Settings” and “Dynamic Reconfiguration” on this PHY IP. Do I would like to alter the parameters in these choices? What parameters must be modified?