Hello crew,

 I’ve tried to verify the pin assignments with design information. I get error for DDR3 alerts I/O Commonplace. 

Initially, I’ve configured the ddr3 I/Os with SSTL-15 CLASS I. after I checked the fitter outcomes, the under errors are reported.

 

Then Reconfigured the alerts with Differential SSTL-15 CLASS I. For that additionally, the under errors are reported.

 

Once I referred the eval board design of cyclone v gt, SSTL-15 CLASS I I/O customary is used. 

are you able to  please assist us to assign the right I/O task in pin