Hello all,

I am making an attempt to carry out a gate-level practical simulation utilizing a FPGA from the Cyclone V household (I do know that gate-level + timing simulations usually are not suported for one of these FPGA), after compiling the design, Quartus generates the .vho file that’s wanted to run one of these simulation, nonetheless, after compiling this file along with the testbench file on ModelSim and working the simulation I do not get any outcomes and all of the outputs stay at 0, does anybody know why?

That is the data I discovered relating to this subject:

https://www.intel.com/content material/www/us/en/docs/programmable/683080/18-1/simulation-levels.html