Home Neural Network Cyclone V De0-Nano SOC – set off seize – latency with Accessing gpio from HPS

Cyclone V De0-Nano SOC – set off seize – latency with Accessing gpio from HPS

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Cyclone V De0-Nano SOC – set off seize – latency with Accessing gpio from HPS

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Good day,

the dev board i’ve is the DE0-Nano-SOC 

5csema4u236cn

 

 

I’m searching for a straightforward and quick technique to give the HPS entry to the GPIO pins. Presently I’ve this circulation setup:

1. click on button on webpage

2. hps saves button state and sends a 1 to the FPGA DigitalOut_1

        -(HPS)  int A =1 -> H2F phrase -> (FPGA) DO_1 = 1 ( takes 1000ms)

3. exterior {hardware} sends a excessive sign 150ms after recieving 1

4. FPGA recieves the excessive sign on DigitalIn_1 line, sends a phrase again to HPS

        – (FPGA) DI_1 = 1 -> F2H phrase -> (HPS)  int B = 1 (takes 1000ms)

 

the issue is that sending indicators throughout the F2h and H2F bus is method too gradual. Is it doable for the HPS to immediately entry and management the DigitalOut/In pins?

 

My present difficulty is that the F2h and H2b bus is method too gradual. Is there a method for the HPS to immediately entry the I/O pins? 

 

the digital pins are related to a pcb that sends a set off again if it sees a excessive sign. the set off solely lasts for about 20ms and is often missed within the F2H window.

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