Hello,

The next error is happening on QSYS of Quartus Prime.

Might you please inform me how one can keep away from the error?

[composition]

QSYS implements CustomPHY (xcvr_custom_phy_0), Reconfig macro (alt_xcvr_reconfig_0), and reset controller (xcvr_reset_controller).

FPGA:Cyclone V GT(5CGTD5)

Quartus Prime model:17.0.0 Construct 595

[Error content]

Synchronization Clock (tx_clkout1) for CustomPHY enter sign pll_powerdown1 can’t be discovered.

[My opinion]

I believe pll_powerdown1 doesn’t must be synchronized with tx_clkout1