Hey,

I’m searching for steering or an instance design that explains configuring the ALTLVDS RX megafunction to be used with a TI 14 bit LVDS ADC. The ADC has 16 LVDS channels, 1 bit clock (DDR) and 1 framing bit. We’re utilizing an Arria 10 SOC. I discovered a youtube video on-line, however as talked about in one other neighborhood put up under, the reference materials doesn’t look like out there. I at present have the ALTLVDS block configured for 7 bit operation and concatenate the 2 7 bit captures, I’m not positive find out how to handle the DDR clock and framing bit. ADC timing diagram is proven under:

Thanks

https://neighborhood.intel.com/t5/FPGA-Mental-Property/Altlvds-RX-Megafunction-in-14-bit-device-mode/m-p/1206521