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Hello,
I received Caught with ad9082 adc path by which jesd hyperlink up will not be developing! am getting kchar, disparity errors , however in the identical design DAC is working !
I’ve compelled the rx_sync sign from jesd ip facet to ad9082 jesd tx (ADC) to determine the difficulty ,On this case standing handed to UDATA from CGS.I’ve hooked up the logs and sign faucet information on your reference.
However In regular working case sync is at all times low and nonetheless I get kchar , disparity errors. I’ve taken an instance design for reference and testing. With jesd(duplex) ip ,DAC hyperlink is okay however ADC hyperlink will not be responding! Please assist us to resolve this.
I do not know what precisely the difficulty is ! whether or not ad9082 Okay char transmission or JESD RX IP receiving!!
Bought caught at this situation for a very long time !! please assist me to resolve this!!!!!
I’m observing identical habits in Stratix10 and Arria10 Dev kits.
Often Clock for ADC is generated by DAC with some divider values. Right here I’m utilizing Duplex ip by which each jesd Transmitter and receiver are blended ,so identical clock for each in FPGA facet. with the identical clock frequency and ranges ,DAC is working positive !
Do ADC clock want any additional energy degree in contrast to DAC clock energy degree ?
Thanks In Advance!!
@jesd204b
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