So I’ve a design which is precisely on this state of affairs :

The one distinction is that the clock is coming from ‘Board Machine’ as properly as a substitute of on the board.

CLK interval is 12.5 ns
Dclock_to_FPGA = 0 ~ 0.1 ns
Ddata = 0 ~ 0.1 ns
Dclock_to_ExtDev = 0 ~ 1ns
Tsetup = 5.8 ns
Thold = 2 ns

So following the formulation :

   Output Delay(max) = 5.8 + 0.1 + 0.1 – 0 = 6 ns
   Output Delay(min) = 0 – 2 + 0 – 1 = -3 ns

Nonetheless, if I take advantage of this within the constraints as follows :

   create_clock -name CLK -period 12.5ns [get_ports {CLK}]
   set_output_delay -clock “CLK” -min -3ns [get_ports {DOUT}]
   set_output_delay -clock “CLK” -max 6ns [get_ports {DOUT}]

This ends in (approx.) 5 ns setup timing violations from REGB to DOUT.

The timing report for considered one of these paths is connected.
Can somebody clarify why this isn’t assembly timing, or what I’m doing unsuitable ?

(Additional information : I additionally made certain that REGB placement is near the CLK / DOUT pins.)

Word that the timing report reveals a Clock Skew of -4.920 ns.
I assume this has one thing to do with it ?

I additionally tried the next settings, however they ALL result in timing failures :

-min 0 / -max 0
     => -1.3 ns violation (skew -6.7 / information delay 7.0 = arrival 13.7 vs. required 12.4 (12.5 – 0 – 0.1)
-min -2 / -max 0
    => -1.2 ns violation (skew -6.7 / information delay 7.0 = arrival 13.7 vs. required 12.4 (12.5 – 0 – 0.1)
-min -5 / -max 0
    => -3.1 ns violation (skew -6.7 / information delay 8.8 = arrival 15.5 vs. required 12.4 (12.5 – 0 – 0.1)
-min -2 / -max 5
    => -4.8 ns violation (skew -4.9 / information delay 6.3 = arrival 11.2 vs. required 6.4 (12.5 – 5 – 0.1)
-min 3 / -max 10
    => -10.7 ns violation (skew -6.8 / information delay 6.2 = arrival 13 vs. required 2.4 (12.5 – 10 – 0.1)
-min 13 / -max 20
    => -20.6 ns violation (skew -6.8 / information delay 6.2 = arrival 13 vs. required -7.6 (12.5 – 20 – 0.1)

So it now looks like I HAVE to make use of a destructive max-delay to fulfill timing ?
How does that make any sense ?