Hello,

There’s a IDC 2*7 on the board, the pins are HPS pins,right here is the schematic

Most of them are connnected to the HPS Bank7. 

In HPS settings, I set the GPIO 58,59,60 as loanIOs(5,7 & 6 of the J32).

I set the IOs as output of the FPGA, and need to management them in my prime layer

HPS setting

Prime layer setting

Quartus setting

bodily connnection(areas are checked appropriate)

Results of the pin, must be test_pulse,which is 0.

however regardless of how I set them, they cannot reply.

The boot methodology is baremetal SPL boot, I dont know whether or not it would affect the useage.

Reguards

Alex