I am utilizing this vhdl code to make an 8 bit counter with allow. Quetasim Intel fpga doesn’t increment the counter repeatedly (outlined as variable).

It goes from ‘X’ to ‘1’ after which it would not rely anymore.
The place am I doing fallacious?
The code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity COUNT8 is

port(

CLK : in std_logic;
EN : in std_logic;
DOUT : out std_logic_vector(7 downto 0)
);

finish COUNT8;

structure habits of COUNT8 is

start
— discover the method assertion and the variable COUNT
clk_proc:course of(CLK)
variable COUNT:std_logic_vector(7 downto 0) := x”00″;
start
if rising_edge(CLK) then
if en = ‘1’ then
COUNT := std_logic_vector((unsigned(COUNT)) + 1);
DOUT <= COUNT;
finish if;
finish if;
finish course of clk_proc;

finish habits;