Hello,

I am utilizing CycloneVsoc dev equipment and wish to use F2SDRAM perform.

I adopted the instruction of neighborhood and examine the CV-FPGA-to-HPS-Bridge-design instance you offered.

I’ve the next questions:

On platform designer:

1.The PLL output clk is 150Mhz.

Why Customized Relaxation Synchronizer enter clock freq shouldn’t be the identical?

2. What does this IP do?

Ive learn the verilog, however my solely understanding is that it delay the reset sign for certern clk cycle.

3. How can I make sure the parameters of that IP are right?

In ARMDS,

There may be some codes about PRBS generater and checker, the place can I get extra data for these two components?

For the instance:

Can I take advantage of the HPS dma do the communication between FPGA and SDRAM?

Reguards

Alex