Earlier (and presumed lifeless) discussions:

https://neighborhood.intel.com/t5/Programmable-Units/Intel-Agilex-FHT-FGT-lane-swapping/m-p/1453468

https://neighborhood.intel.com/t5/Intel-Quartus-Prime-Software program/Aglix-F-tile-P-amp-R-error/m-p/1456868

Been making an attempt to drive alerts out the QSFP-DD cages on my Agilex 027 SoC evm.  Quartus is complaining in regards to the pin assignments after I configure a quad of outputs (one occasion, 4 lanes) in Platform Designer.  The pins in query, from the SoC evm schematic:

I turned on all 16 FGT transceivers in an F-Tile to see the place the compiler needed to position them.  This is the breakdown of mappings from core alerts to I/O pins:

All 16 FGT transceivers assigned.  Pins chosen by Quartus (no constraints in .qsf)
qsfpdd0_tx0	Output		PIN_AD7		 Quad3[0]
qsfpdd0_tx1	Output		PIN_AG10	 Quad3[1]
qsfpdd0_tx2	Output		PIN_AH7		 Quad3[2]
qsfpdd0_tx3	Output		PIN_AM7		 Quad3[3]
hssi4p	Output			PIN_AC10	Quad2[3]
hssi5p	Output			PIN_Y7		Quad2[2]
hssi6p	Output			PIN_W10		Quad2[1]
hssi7p	Output			PIN_T7		Quad2[0]
hssi8p	Output			PIN_R10		 Quad1[3]
hssi9p	Output			PIN_M7		 Quad1[2]
hssi10p	Output			PIN_L10		 Quad1[1]
hssi11p	Output			PIN_G10		 Quad1[0]
hssi12p	Output			PIN_H13		Quad0[3]
hssi13p	Output			PIN_D13		Quad0[2]
hssi14p	Output			PIN_G16		Quad0[1]
hssi15p	Output			PIN_C16		Quad0[0]

Observe that bits out[3:0] map to Quad3[3:0] however
out[7:4] map to Quad2[0:3] - bus twist
out[11:8] map to Quad1[0:3] - bus twist
out[15:12] map to Quad0[0:3] - bus twist

Seems there’s bus twist on the Tile stage, then once more on the Quad stage.  So, “bus twist”?  Wazzat? 

Usually, it is a head-butting of big-endian and little-endian views.  Easy verilog instance that assigns one 8-bit bus to a different:

Abus[7:0] <= Bbus[0:7];

No massive deal, proper?  The values of Bbus acquired assigned to Abus.  What’s actually taking place:

Abus[7] <= Bbus[0];
Abus[6] <= Bbus[1];
Abus[5] <= Bbus[2];
Abus[4] <= Bbus[3];
Abus[3] <= Bbus[4];
Abus[2] <= Bbus[5];
Abus[1] <= Bbus[6];
Abus[0] <= Bbus[7];

I am working Quartus Professional 23.3, however this was noticed in 23.1 and 22.3.  If I attempt to map my output qsfp_dd[0] to pin T7 (which is FGTR13C_TX_Q2_CH0p) I’ll get an error saying there is no useful resource obtainable or that the sign have to be mapped to a unique set of internally-named pins with a [3] suffix.  If I twist my bus outputs such that out[3] is mapped to FGT_CH0p, it connects simply positive.  Notably, I did NOT have this subject with an Agilex AGF014 eval board that I used to be utilizing beforehand.  That one used E-Tiles, so this is likely to be particular to the F-Tile implementation.

This kind of downside is frequent for bussed alerts (vectors) that cross a hierarchy boundary and the top-level and bottom-level declarations have reverse endian-ness. 

I am simply going to patch round this subject with a macro-reassignment at my top-level that spackles-over the twist.  Can be good is Altera may repair the supply subject in Quartus.