L-Tile/H-Tile Transcever ATX PLL Intel Sttratix 10 FPGA IP utilized by PLL. The configured parameters are as proven within the determine under：

However in the course of the FIT stage there shall be an error as proven under：

 My PHY is utilizing L-Tile/H-Tile Transcever Native PHY Intel Stratix 10FPGA IP,set the VCCR_GXB and VCCT_GXB  provide voltage for the transceiver to 1_0V, choose GXT for transceiver channel sort ,choose Fundamental(Enhanced PCS) for Transceiver configuration guidelines, and set Information fee to 16000M. Use the default parameters for the remainder of the settings.