So the exterior system is simply combinatorial logic or does it even have enter and output registers?

If it is simply logic (not clocked), you may in all probability use set_max_delay and set_min_delay between the output and enter ports to outline all of the exterior delay.  Simply add up the hint delays and tco (is it referred to as tco within the system’s spec however not clocked?  Hmm.) to give you values.

Or are you saying that the FPGA clocks the exterior system which then sends a worth again to the FPGA?  In that case, that is a suggestions design, so that you’d have to outline the output clock from the FPGA as a generated clock, set the output port as a false path so it isn’t analyzed as an information output, and use set_input_delay on the enter, referencing the output clock and setting max/min values primarily based on the overall hint and tco delay via the exterior system.