Hey,

     I discovered that the hyperlink information and pcs information are inconsistent. the UG show system clock needs to be on the similar frequency because the hyperlink clock, however I did not discover it earlier than. In my design, F, M, L = 8, 16, 4, and the speed of every lane is 8G, however I set the system clocks of ADC and FPGA at 100M, the core pll shares the system clock with the jesd204b IP, and outputs a 200M hyperlink clock and a 100M body clock. jesd204b IP outputs 128bit hyperlink information and 256bit body information.I’m not positive if the system clk frequency or different causes trigger the info inconsistency, is there any resolution?

thanks！