Whats up everybody, I’ve put in Quartus in debian, and once I simulate in “College Program VWF” it will get caught and doesn’t end the method. The reality is that I do not know tips on how to resolve it, please I need assistance.

Figuring out the placement of the ModelSim executable…

Utilizing: /residence/manuel/intelFPGA_lite/19.1/modelsim_ae/linuxaloem/

To specify a ModelSim executable listing, choose: Instruments -> Choices -> EDA Instrument Choices
Observe: if each ModelSim-Altera and ModelSim executables can be found, ModelSim-Altera shall be used.

**** Producing the ModelSim Testbench ****

quartus_eda –gen_testbench –tool=modelsim_oem –format=vhdl –write_settings_files=off reg_s_p1 -c reg_s_p1 –vector_source=”/residence/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/Waveform7.vwf” –testbench_file=”/residence/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/Waveform7.vwf.vht”

Data: *******************************************************************Data: Working Quartus Prime EDA Netlist Author Data: Model 19.1.0 Construct 670 09/22/2019 SJ Lite Version Data: Copyright (C) 2019 Intel Company. All rights reserved. Data: Your use of Intel Company’s design instruments, logic features Data: and different software program and instruments, and any associate logic Data: features, and any output information from any of the foregoing Data: (together with machine programming or simulation information), and any Data: related documentation or data are expressly topic Data: to the phrases and situations of the Intel Program License Data: Subscription Settlement, the Intel Quartus Prime License Settlement, Data: the Intel FPGA IP License Settlement, or different relevant license Data: settlement, together with, with out limitation, that your use is for Data: the only function of programming logic units manufactured by Data: Intel and bought by Intel or its licensed distributors. Please Data: discuss with the relevant settlement for additional particulars, at Data: https://fpgasoftware.intel.com/eula. Data: Processing began: Mon Mar 18 01:01:27 2024Info: Command: quartus_eda –gen_testbench –tool=modelsim_oem –format=vhdl –write_settings_files=off reg_s_p1 -c reg_s_p1 –vector_source=”/residence/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/Waveform7.vwf” –testbench_file=”/residence/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/Waveform7.vwf.vht”Warning (18236): Variety of processors has not been specified which can trigger overloading on shared machines. Set the worldwide task NUM_PARALLEL_PROCESSORS in your QSF to an acceptable worth for greatest efficiency.

Accomplished efficiently.

**** Producing the useful simulation netlist ****

quartus_eda –write_settings_files=off –simulation –functional=on –flatten_buses=off –tool=modelsim_oem –format=vhdl –output_directory=”/residence/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/” reg_s_p1 -c reg_s_p1

Data: *******************************************************************Data: Working Quartus Prime EDA Netlist Author Data: Model 19.1.0 Construct 670 09/22/2019 SJ Lite Version Data: Copyright (C) 2019 Intel Company. All rights reserved. Data: Your use of Intel Company’s design instruments, logic features Data: and different software program and instruments, and any associate logic Data: features, and any output information from any of the foregoing Data: (together with machine programming or simulation information), and any Data: related documentation or data are expressly topic Data: to the phrases and situations of the Intel Program License Data: Subscription Settlement, the Intel Quartus Prime License Settlement, Data: the Intel FPGA IP License Settlement, or different relevant license Data: settlement, together with, with out limitation, that your use is for Data: the only function of programming logic units manufactured by Data: Intel and bought by Intel or its licensed distributors. Please Data: discuss with the relevant settlement for additional particulars, at Data: https://fpgasoftware.intel.com/eula. Data: Processing began: Mon Mar 18 01:01:28 2024Info: Command: quartus_eda –write_settings_files=off –simulation=on –functional=on –flatten_buses=off –tool=modelsim_oem –format=vhdl –output_directory=”/residence/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/” reg_s_p1 -c reg_s_p1Warning (18236): Variety of processors has not been specified which can trigger overloading on shared machines. Set the worldwide task NUM_PARALLEL_PROCESSORS in your QSF to an acceptable worth for greatest efficiency.Data (204019): Generated file reg_s_p1.vho in folder “/residence/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim//” for EDA simulation toolInfo: Quartus Prime EDA Netlist Author was profitable. 0 errors, 1 warning Data: Peak digital reminiscence: 1101 megabytes Data: Processing ended: Mon Mar 18 01:01:28 2024 Data: Elapsed time: 00:00:00 Data: Whole CPU time (on all processors): 00:00:00

Accomplished efficiently.

**** Producing the ModelSim .do script ****

/residence/manuel/Documentos/Quartus initiatives/ejemplo2/reg_s_p1/simulation/qsim/reg_s_p1.do generated.

Accomplished efficiently.

**** Working the ModelSim simulation ****

/residence/manuel/intelFPGA_lite/19.1/modelsim_ae/linuxaloem//vsim -c -do reg_s_p1.do