Hiya everybody,

I am utilizing a DE0 Nano SoC, and I’ve a PLL that gives me with a frequency of 500 MHz. I need to generate pulse bursts on my GPIO connector. Thus far, I can create pulses with a length of 2n, and all the things works very nicely. The difficulty is that with a frequency of 500 MHz, I can solely shift my sign each 2 ns.

Subsequently, I want to implement a Time Digital Converter (TDC) so as to add a delay and be capable to shift the sign by 250 ps and/or 500 ps and/or 1 ns. Truly, the precision of the timing would not matter a lot. What I need to perceive is the methodology, the way it’s finished.

I’ve seen in publications and elsewhere that there are two steps. The primary is to create this delay chain, utilizing code? A drawing in Quartus?

The second step is to manually place the “blocks” in chip planner. It appears to me that we are able to merely drag and drop these blocks, and the objective is to place them in collection to manage the delay. However how can we perceive these blocks? They’re fairly sophisticated.

Additionally, from what I’ve seen elsewhere, our counterparts use carry4. Do we’ve an equal?

Determine 1 : what I need to do (is that this right?)

Determine 2 : Satan block

Final thing: can we observe this delay in simulation? What pursuits me is solely the measurement on the GPIO connector, however I do not at all times have the metrology with me, whereas a pc does.

Thanks for studying.