Hello, i wrote my code for a 3 to eight decoder in structural vhdl :

i had no issues through the compilation. When i attempted to simulate to see the outcomes, it says :

 **** Operating the ModelSim simulation **** c:/altera/13.1/modelsim_ase/win32aloem//vsim -c -do Laboratoire2.do Studying C:/altera/13.1/modelsim_ase/tcl/vsim/pref.tcl # 10.1d # do Laboratoire2.do # ** Warning: (vlib-34) Library already exists at “work”. # # Mannequin Expertise ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 # — Compiling module DECODEUR_3_x_8 # # Prime stage modules: # DECODEUR_3_x_8 # Mannequin Expertise ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 # — Compiling module DECODEUR_3_x_8_vlg_sample_tst # ** Error: Simulation_decodeur_3_x_8.vwf.vt(30): close to “,”: syntax error, sudden ‘,’ # ** Error: c:/altera/13.1/modelsim_ase/win32aloem/vlog failed. # Executing ONERROR command at macro ./Laboratoire2.do line 4 Error.

I by no means had this error earlier than. I opened the file Simulation_decodeur_3_x_8.vwf.vt and that i didnt see any errors. I uploaded the code of the decodeur and the simulation one. Are you able to assist me ?